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V rms × I rms × ? 1 +
? VAGAIN Register ? (41)
2 23
ADE7854/ADE7858/ADE7868/ADE7878
Apparent Power Gain Calibration
The average apparent power result in each phase can be scaled
by ±100% by writing to one of the phase’s VAGAIN 24-bit registers
(AVAGAIN, BVAGAIN, or CVAG AIN). The VAGAIN registers
are twos complement, signed registers and have a resolution of
2 ?23 /LSB. The function of the xVAGAIN registers is expressed
mathematically as
Average Apparent Power =
?
? ?
The output is scaled by –50% by writing 0xC00000 to the
xVAGAIN registers, and it is increased by +50% by writing
0x400000 to them. These registers calibrate the apparent power
ADE7878 for each phase.
section, the serial ports of the ADE78xx work on 32-, 16-, or 8-bit
words and the DSP works on 28 bits. Similar to registers presented
in Figure 35, the AVAGAIN, BVAGAIN, and CVAGAIN 24-bit
registers are accessed as 32-bit registers with the four MSBs
padded with 0s and sign extended to 28 bits.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register
to calibrate and eliminate the dc component in the rms value
(see the Root Mean Square Measurement section). The voltage
Data Sheet
As stated in the Current Waveform Gain Registers, the serial
ports of the ADE78xx work on 32-, 16-, or 8-bit words. Similar
to the register presented in Figure 36, the VNOM 24-bit signed
register is accessed as a 32-bit register with the eight MSBs
padded with 0s.
Apparent Energy Calculation
Apparent energy is defined as the integral of apparent power.
Apparent Energy = ∫ s ( t ) dt (43)
signal in two stages (see Figure 73). The first stage is conducted
inside the DSP: every 125 μs (8 kHz frequency), the instanta-
neous phase apparent power is accumulated into an internal
register. When a threshold is reached, a pulse is generated at the
processor port and the threshold is subtracted from the internal
register. The second stage is conducted outside the DSP and
consists of accumulating the pulses generated by the processor
into internal 32-bit accumulation registers. The content of these
registers is transferred to the VA-hour registers, xVAHR, when
Calculation section illustrates this process. The VATHR 48-bit
register contains the threshold. Its value depends on how much
energy is assigned to one LSB of the VA-hour registers. When a
derivative of apparent energy (VAh) of [10 n VAh], where n is an
integer, is desired as one LSB of the xVAHR register; then, the
xVATHR register can be computed using the following equation:
and current rms values are multiplied together in the apparent
power signal processing. As no additional offsets are created in
the multiplication of the rms values, there is no specific offset
VATHR =
PMAX × f s × 3600 × 10 n
V FS × I FS
VNOM =
× 4 , 191 , 910
V
ApparentEn ergy = ∫ s ( t ) dt = Lim ? ∑ s ( nT ) × T ?
(44)
compensation in the apparent power signal processing. The offset
compensation of the apparent power measurement in each phase is
accomplished by calibrating each individual rms measurement.
Apparent Power Calculation Using VNOM
The ADE7854 / ADE7858 / ADE7868 / ADE7878 can compute the
apparent power by multiplying the phase rms current by an rms
voltage introduced externally in the VNOM 24-bit signed register.
When one of Bits[13:11] (VNOMCEN, VNOMBEN, or
VNOMAEN) in the COMPMODE register is set to 1, the
apparent power in the corresponding phase (Phase x for
VNOMxEN) is computed in this way. When the VNOMxEN
bits are cleared to 0, the default value, then the arithmetic
apparent power is computed.
The VNOM register contains a number determined by V, the
desired rms voltage, and V FS , the rms value of the phase voltage
when the ADC inputs are at full scale:
(42)
V FS
where V is the desired nominal phase rms voltage.
where:
PMAX = 33,516,139 = 0x1FF6A6B, the instantaneous power
computed when the ADC inputs are at full scale.
f S = 8 kHz, the frequency with which the DSP computes the
instantaneous power.
V FS , I FS are the rms values of phase voltages and currents when
the ADC inputs are at full scale.
VATHR is a 48-bit register. As previously stated in the Current
Similar to the WTHR register presented in Figure 69, the VATHR
register is accessed as two 32-bit registers (VATHR1 and VATHR0),
each having eight MSBs padded with 0s.
This discrete time accumulation or summation is equivalent to
integration in continuous time following the description in
Equation 44.
? ∞ ?
T → 0 ? n = 0 ?
where:
n is the discrete time sample number.
T is the sample period.
Rev. H | Page 58 of 100
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